This invention relates to density improvement in a patterned-overlay, Hybrid Wafer-Scale Integration (HWSI) module by replacing the individual dies with chip-like stacks of thinned dies. While conventional hybrid wafer-scale integration allows chip dies to be placed edge-to-edge, this does not achieve desired compactness. A "die" is a chip-like portion separated from a larger integrated circuit structure.
There is a need for packaging memory dies more compactly to support the development of a wafer-scale vector or signal processor WSVP or WSSP. Each element in an illustrative WSVP requires 16 memory dies and one processor die. If a conventional two-dimensional HWSI module is used in each processor, the element would require an area of about four square inches, of which about 16/19 of the area would be occupied by memory dies. This would result in interconnects as long as four inches, and would unacceptably slow the memory transferred to a central processor unit (CPU) interface.
An objective of the invention is to place at least four processor elements into a four square inch area, not just one.
"Sugar cube" memories are so-called because each memory element describes a lump of sugar. They are described in U.S. Pat. No. 4,525,921 (Carson et al.) and U.S. Pat. No. 4,617,160 (Belanger et al.) with stacked memories horizontally mounted on top of a HWSI substrate. This approach saves area, but introduces a "skyline" effect that inhibits the stacking of HWSI modules.